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HIP4081
November 1996
80V/2.5A Peak, High Frequency Full Bridge FET Driver
Description
The HIP4081 is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081 can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081 can switch at frequencies up to 1MHz andssssss is well suited to driving Voice Coil Motors, high-frequency Class D audio amplifiers, and power supplies. For example, the HIP4081 can drive medium voltage brush motors, and two HIP4081s can be used to drive high performance stepper motors, since the short minimum "on-time" can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. A similar part, the HIP4080, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate "hysteresis mode" switching. See Application Note AN9325 for HIP4081, Intersil AnswerFAX, (407) 724-7800, document #99325. Intersil web home page: http://www.semi.intersil.com Similar part HIP4081A includes undervoltage circuitry which does not require the circuitry shown in Figure 30 of this data sheet.
PACKAGE 20 Lead Plastic DIP 20 Lead Plastic SOIC PKG. NUMBER E20.3 M20.3
Features
* Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations * Bootstrap Supply Max Voltage to 95VDC * Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns * User-Programmable Dead Time * On-Chip Charge-Pump and Bootstrap Upper Bias Supplies * DIS (Disable) Overrides Input Control * Input Logic Thresholds Compatible with 5V to 15V Logic Levels * Very Low Power Consumption
Applications
* Medium/Large Voice Coil Motors * Full Bridge Power Supplies * Class D Audio Power Amplifiers * High Performance Motor Controls * Noise Cancellation Systems * Battery Powered Vehicles * Peripherals * U.P.S.
Ordering Information
PART NUMBER HIP4081IP HIP4081IB TEMP. RANGE (oC) -40 to 85 -40 to 85
Pinout
HIP4081 (PDIP, SOIC) TOP VIEW
BHB BHI DIS VSS BLI ALI AHI HDEL LDEL 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 BHO BHS BLO BLS VDD VCC ALS ALO AHS AHO
AHB 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3556.7
1
HIP4081 Application Block Diagram
80V
12V BHO BHS BHI BLI HIP4081 ALI AHI ALO AHS AHO BLO LOAD
GND
GND
Functional Block Diagram (1/2 HIP4081)
HIGH VOLTAGE BUS 80VDC AHB 10 CHARGE PUMP VDD 16 AHI 7 TURN-ON DELAY DBS DIS 3 15 VCC TO VDD (PIN 16) LEVEL SHIFT AND LATCH DRIVER 11 AHS 12 AHO CBS
DRIVER ALI 6 TURN-ON DELAY 13
ALO CBF
+12VDC BIAS SUPPLY
ALS 14 HDEL LDEL VSS 8 9 4
2
HIP4081 Typical Application (PWM Mode Switching)
80V
1 BHB 12V DIS PWM INPUT 2 BHI 3 DIS 4 VSS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB
BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11 12V LOAD
GND TO OPTIONAL CURRENT CONTROLLER
+ 6V
GND
3
HIP4081
Absolute Maximum Ratings
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +16V Voltage on ALO, BLO . . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All voltages are relative to pin 4, VSS, unless otherwise specified.
Thermal Information
(Typical, Note 1)
Storage Temperature Range . . . . . . . . . . . . . . . . . . .-65oC to 150oC Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300oC (For SOIC - Lead Tips Only) Thermal Resistance, Junction-Ambient SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85oC/W DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . +6V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500A to -50A Operating Ambient Temperature Range . . . . . . . . . . .-40oC to 85oC
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified TJ = 25oC TJS = -40oC TO 125oC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX MIN MAX UNITS
SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current VDD Operating Current VCC Quiescent Current VCC Operating Current AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL, VLDEL IHDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V IIL IIH VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions VIL VIH Full Operating Conditions Full Operating Conditions 2.5 35 1.0 -75 +1 2.7 -135 -10 0.8 -65 +10 V V mV A A IDD IDDO ICC ICCO IAHB, IBHB All Inputs = 0V Outputs Switching f = 500kHz All Inputs = 0V, IALO = IBLO = 0 f = 500kHz, No Load All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V 7 8 1 -50 0.5 11.5 9 9.5 0.1 1.25 -30 0.9 0.02 12.6 11 12 10 2.0 -15 1.3 1.0 14.0 6 7 0.8 -60 0.4 10.5 12 13 20 3 -10 1.7 10 14.5 mA mA A mA A mA A V
IAHBO, IBHBO f = 500kHz, No Load IHLK VAHB-VAHS VBHB-VBHS VAHS = VBHS = VAHB = VBHB = 95V IAHB = IAHB = 0, No Load
-130 -100 -1 -
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage High Level Output Voltage VOL VCC -VOH IOUT = 100mA IOUT = -100mA 0.7 0.8 0.85 .95 1.0 1.1 0.5 0.5 1.1 1.2 V V
4
HIP4081
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) TJ = 25oC PARAMETER Peak Pullup Current Peak Pulldown Current SYMBOL IO+ IOTEST CONDITIONS VOUT = 0V VOUT = 12V MIN 1.7 1.7 TJS = -40oC TO 125oC
TYP MAX MIN MAX UNITS 2.6 2.4 3.8 3.3 1.4 1.3 4.1 3.6 A A
Switching Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF TJ = +25oC TJS = 40oC TO 125oC MIN 50 40 140 MAX UNITS 80 90 90 110 35 35 95 105 90 420 550 ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) Rise Time Fall Time Turn-on Input Pulse Width Turn-off Input Pulse Width Disable Turn-off Propagation Delay (DIS - Lower Outputs) Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO)
SYMBOL TLPHL THPHL TLPLH THPLH TR TF TPWIN-ON TPWIN-OFF TDISLOW TDISHIGH TDLPLH TREF-PW THEN
TEST CONDITIONS
MIN 50 40 160 -
TYP 30 35 45 60 10 10 45 55 35 260 335
MAX 60 70 70 90 25 25 75 85 70 380 500
TRUTH TABLE INPUT ALI, BLI X 1 0 0 AHI, BHI X X 1 0 DIS 1 0 0 0 ALO, BLO 0 1 0 0 OUTPUT AHO, BHO 0 0 1 0
NOTE: X signifies that input can be either a "1" or "0".
5
HIP4081 Pin Descriptions
PIN NUMBER 1 SYMBOL BHB DESCRIPTION B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. Disable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold DIS high if this pin is not driven. Chip negative supply, generally will be ground. B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold BLI high if this pin is not driven. A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold ALI high if this pin is not driven. A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. A High-side Output. Connect to gate of A High-side power MOSFET. A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. A Low-side Output. Connect to gate of A Low-side power MOSFET. A Low-side Source connection. Connect to source of A Low-side power MOSFET. Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). B Low-side Source connection. Connect to source of B Low-side power MOSFET. B Low-side Output. Connect to gate of B Low-side power MOSFET. B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. B High-side Output. Connect to gate of B High-side power MOSFET.
2
BHI
3
DIS
4 5
VSS BLI
6
ALI
7
AHI
8
HDEL
9
LDEL
10
AHB
11 12 13 14 15 16 17 18 19 20
AHO AHS ALO ALS VCC VDD BLS BLO BHS BHO
6
HIP4081 Timing Diagrams
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL DIS = 0 XLI THPHL
XHI
XLO
XHO
THPLH
TLPLH
TR (10% - 90%)
TF (10% - 90%)
FIGURE 1.
INDEPENDENT MODE
DIS = 0 XLI
XHI = HI OR NOT CONNECTED
XLO
XHO
FIGURE 2. BISTATE MODE
TDLPLH TREF-PW
TDIS
DIS
XLI
XHI
XLO
XHO THEN
FIGURE 3. DISABLE FUNCTION
7
HIP4081 Typical Performance Curves
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified
11.0 10.5 SUPPLY CURRENT (mA) 6 8 10 12 14 10.0 9.5 9.0 8.5 8.0 0 100 200 300 400 500 600 700 800 900 1000 VDD SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (kHz)
14.0 IDD SUPPLY CURRENT (mA) 12.0 10.0 8.0 6.0 4.0 2.0
FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE
FLOATING SUPPLY BIAS CURRENT (mA) 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)
FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz)
5.0 125oC ICC SUPPLY CURRENT (mA) 4.0 75oC 25oC 3.0 0oC -40oC 2.0
1.0
0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF)
FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE
FLOATING SUPPLY BIAS CURRENT (mA)
-90 LOW LEVEL INPUT CURRENT (A) 1.8
1.4
-100
1.0
0.6
-110
0.2
-0.2 0 200 400 600 800 1000 SWITCHING FREQUENCY (kHz)
-120 -50
-25
0
25
50
75
100
125
JUNCTION TEMPERATURE (oC)
FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY CURRENT vs FREQUENCE
FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE
8
HIP4081 Typical Performance Curves
15.0 NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)
80
PROPAGATION DELAY (ns) -20 0 20 40 60 80 100 120
14.0
70
13.0
60
12.0
50
11.0
40
10.0 -40
30 -40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE
FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE
80
400
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns) -20 0 20 40 60 80 100 120
380
70
360
60
340
50
320
40
300 -40
30 -40 -20 0 JUNCTION TEMPERATURE (oC) 20 40 60 80 JUNCTION TEMPERATURE (oC) 100 120
FIGURE 12. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE
FIGURE 13. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE
375 REFRESH PULSE WIDTH (ns)
80 70 60 50 40 30 20 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)
325
275
225
175
FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE
FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE
9
PROPAGATION DELAY (ns)
HIP4081 Typical Performance Curves
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)
80 70 60 50 40 30 20 -40 -20 0 20 40 60 80 JUNCTION TEMPERATURE (oC) 100 120
80 70 60 50 40 30 20 -40
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
-20
0
20 40 60 80 JUNCTION TEMPERATURE (oC)
100
120
FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE
FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE
80 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) -40 -20 0 20 40 60 80 100 120 70 60 50 40 30 20 JUNCTION TEMPERATURE (oC)
80 70 60 50 40 30 20 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC)
FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE
FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE
13.5
13.5
GATE DRIVE FALL TIME (ns)
11.5
TURN-ON RISE TIME (ns)
12.5
12.5
11.5
10.5
10.5
9.5
9.5
8.5 -40
-20
0
20 40 60 80 JUNCTION TEMPERATURE (oC)
100
120
8.5 -40
-20
0
20 40 60 80 JUNCTION TEMPERATURE (oC)
100
120
FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE
FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE
10
HIP4081 Typical Performance Curves
6.0 HDEL, LDEL INPUT VOLTAGE (V)
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)
1500
1250 5.5 VCC - VOH (mV) 1000 -40oC 0oC 500 25oC 75oC 125oC 4.0 -40 -20 0 20 40 60 80 100 120 0 6 8 10 12 14 BIAS SUPPLY VOLTAGE (V)
5.0
750
4.5 250
JUNCTION TEMPERATURE (oC)
FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE
FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA
1500 GATE DRIVE SINK CURRENT (A) -40oC 1250 0oC 1000 VOL (mV) 750 500 250 0 6 8 10 12 BIAS SUPPLY VOLTAGE (V) 14
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 6 7 8 9 10 11 12 13 VDD , VCC , VAHB , VBHB (V) 14 15 16
25oC 75oC 125oC
FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERTURE AT 100mA
3.5
FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE
500 LOW VOLTAGE BIAS CURRENT (mA) 200 100 50 20 10 5 2 1 0.5 0.2 0.1 1 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) 10,000pF 3,000pF 1,000pF 100pF
GATE DRIVE SINK CURRENT (A)
3.0 2.5 2.0 1.5 1.0 0.5 0.0 6 7 8 9 10 11 12 13 14 15 16 VDD , VCC , VAHB , VBHB (V)
FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY VOLTAGE
FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE
11
HIP4081 Typical Performance Curves
1000 500 LEVEL-SHIFT CURRENT (A) 120 200 100 50 20 10 5 2 1 1 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) 80V 60V 40V 20V 0 10 50 100 150 200 250 HDEL/LDEL RESISTANCE (k) DEAD-TIME (ns) 90
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)
150
60
30
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE
FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE
HI4081 Power-up Application Information
The HIP4081 H-Bridge Driver IC requires external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. The HIP4081 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the DIS pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 30. As the VDD /VCC supply ramps from zero up, the DIS voltage is below its input threshold of 1.7V due to the R1/R2 resistor divider. When VDD /VCC exceeds approximately 9V to 10V, DIS becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to DIS reaching its threshold level of 1.7V while VDD /VCC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the DIS pin low.
R1 15K
1 BHB 2 BHI 3 DIS
BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11
ENABLE R2 3.3K
4 VSS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB
FIGURE 30A.
VDD
12V, FINAL VALUE 8.5V TO 10.5V (ASSUMES 5% RESISTORS)
ALI, BLI
DIS 1.7V
t1
NOTES: 2. ALI and/or BLI may be high after t1, whereupon the ENABLE pin may also be brought high. 3. Another product, HIP4081A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry. FIGURE 30B. TIMING DIAGRAM FOR FIGURE 30A
12
IN2 IN1
+12V
POWER SECTION B+
R29
JMPR5
CONTROL LOGIC SECTION
Q1 + C6 DRIVER SECTION CR2 HIP4080/81 C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 4V SS 5 OUT/BLI 6 IN+/ALI 7 IN-/AHI 8 HDEL R33 R34 3 IN-/AHI 2 CW 1 2 CW 1 3 CR1 C3 CX C5 CY 9 LDEL 10 AHB BLS 17 16 V VCC 15 ALS 14 ALO 13 AHS 12 AHO 11
DD
2
C8
R21
1 3 1 Q3 2
1
U2 CD4069UB
2
JMPR1
OUT/BLI
U1
R22 3 L1 AO +12V Q2 2 R23 1 3 Q4 R24 1 2 C1 L2 BO C2
13
U2 CD4069UB
12
JMPR2
IN+/ALI
5
U2 CD4069UB
6
JMPR3 HEN/BHI
11
U2 CD4069UB
10
JMPR4
HIP4081
3
13
ENABLE IN I R32 3 U2 4 O 15K CD4069UB 9 U2 8 3.3K O CD4069UB
R30
R31 COM
ALS TO DIS PIN
BLS
NOTES: 4. Device CD4069UB PIN 7 = COM, Pin 14 = +12V. 5. Components L1, L2, C1, C2, CX, CY, R30, R31, not supplied. refer to Application Note for description of input logic operation to determine jumper locations for JMPR1 - JMPR4. FIGURE 31. HIP4081 EVALUATION BOARD SCHEMATIC
GND
+12V
B+ R28 R26
COM
JMPR5
R29
R27
C7
C8 C6 CR2 Q1 U1 C4 BHO HIP4080/81 BLO BLS Q2 1 R21 Q4 1 R22 R24 L1 L2 1 Q3 1 +
C1
+ R32
AO
U2 IN1 I O IN2
DIS
JMPR1 JMPR2 JMPR3 JMPR4
C2
BO
HIP4081
ALS ALO AHO
HDEL
C5
CX
ALS
CR1 R33 R34
R30
CY
BLS
FIGURE 32. HIP4081 EVALUATION BOARD SILKSCREEN
R31
14
R23
O LDEL
C3
HIP4081 Supplemental Information for HIP4080 and HIP4081 Power Application
The HIP4080 and HIP4081 H-Bridge Driver ICs require external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shootthrough current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. HIP4081 The HIP4081 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the DIS pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 33. As the VDD/VCC supply ramps from zero up, the DIS voltage is below its input threshold of 1.7V due to the R1/R2 resistor divider. When VDD/VCC exceeds approximately 9V to 10V, DIS becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to DIS reaching its threshold level of 1.7V while VDD/VCC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the DIS pin low. HIP4080 The HIP4080 does not have an input protocol like the HIP4081 that keeps both lower power MOSFETs off other than through the DIS pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming DIS is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure 34. Pulling LDEL to VDD will indefinitely delay the lower turn-on delays through the input comparator and will keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled, i.e., DIS = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure 33.
R1 15K
1 BHB 2 BHI 3 DIS
BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11
ENABLE R1 15K
1 BHB 2 BHI 3 DIS
BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11
ENABLE R2 3.3K
4 VSS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB
R2 3.3K
4 VSS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB
FIGURE 33.
1 BHB VDD VDD ENABLE 56K 2N3906 56K 8.2V VDD 100K 100K 0.1F RDEL RDEL 2 HEN 3 DIS 4 VSS 5 OUT 6 IN+ 7 IN8 HDEL 9 LDEL 10 AHB
BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11
FIGURE 34.
15
HIP4081 Timing Diagrams
VDD VDD 12V, FINAL VALUE 8.5V TO 10.5V (ASSUMES 5% RESISTORS) ALI, BLI LDEL DIS 1.7V t1 =10ms t2 5.1V DIS 12V, FINAL VALUE 8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)
NOTE: 6. ALI and/or BLI may be high after t1, whereupon the ENABLE pin may also be brought high.
NOTE: 7. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If the ENABLE pin is low after the undervoltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+ and IN- pins must cycle at least once. FIGURE 36.
FIGURE 35.
16
HIP4081 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.55 0.204 24.89 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 26.9 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.980 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 1.060 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 20 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 20
2.93
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HIP4081 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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